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| Output Logic Type: LVPECL |
| Frequency Range: 10.0MHz to 1450MHz |
| Load: Differential |
| Power Supply Voltage: 2.5±5%VDC or +3.3±10%VDC |
| Output Voltage 'HIGH': VDD - 1.03V minimum VDD - 0.6V maximum |
| Output Voltage 'LOW': VDD - 1.85V minimum VDD - 1.6V maximum |
| Frequency Stability: ±50ppm over -40° to +85°C* |
| Duty Cycle: 50%±2% |
| Rise Time: 150ps minimum** |
| Fall Time: 250ps maximum** |
| Current Consumption @+2.5VDD |
| 100.000MHz: 46mA 250.000MHz: 48mA 500.00MHz: 53mA 750.00MHz: 56mA 1GHz: 60mA 1.35GHz: 65mA |
| Current Consumption @+3.3VDD |
| 100.000MHz: 48mA 250.000MHz: 50mA 500.00MHz: 55mA 750.00MHz: 59mA 1GHz: 62mA 1.35GHz: 68mA |
| Current with output disabled: 16mA typical |
| Start-up Time: 10ms maximum |
| Ageing: ±2ppm max., first year, ±10ppm max. over 10 years. |
| OE Control on Pad 1 Enable: 0.7% VDD min., or no connection Disable: 0.3%VDD max., (high impedance). |
| Output Enable Time: 200ns max. |
| Output Disable Time: 50ns max |
| Phase Jitter r.m.s.: 0.6ps typical (12kHz to 20MHz) <100fs (1.875MHz to 20MHz |